Mainstream memory technologies today are based primarily on some variation of a CMOS process. As advanced CMOS memory processes are being developed below the 65 nanometer point, the ability to shrink a technology to the next sub-micron geometry to achieve more performance and density is expected to reach its practical limits sometime in the next 10-15 years. Potential existing technology replacement candidates may be in a research facility today with much work left, or they could be proceeding down the road to mass commercialization. This service provides forecasts of revenue potentials in the next five years and the following ten years for potential new memory types.